1. Field of the Invention
The present invention relates to a method of detecting a defect of a semiconductor integrated circuit and an apparatus thereof. In particular, the invention relates to a method of detecting a defect of a semiconductor integrated circuit in which electron beam (hereinafter referred to as "EB") is irradiated from the rear side of a semiconductor substrate of the semiconductor integrated circuit to observe it, as well as an apparatus thereof.
2. Description of the Background Art
Recently, the need for higher detectivity and efficiency of defect detection has become increasingly important in the fault analytic techniques of semiconductor integrated circuits. To detect a defect of an integrated circuit having more large scale, multi-layer, and high-level function, it is necessary to inspect not only failure information obtained from signals that are outputted outside from an integrated circuit but also information related to signals transferred within the integrated circuit. As an example of semiconductor analyzers to make such inspection, there are EB testers in which EB serves as a probe and the potential waveform and potential contrast image of an internal metal wire in a semiconductor integrated circuit as a device under test are observed in non-contact manner. That is, the EB testers are a semiconductor analyzer in which the potential states of wires constituting a semiconductor integrated circuit are observed while operating the circuit. In order to detect a defect on the inside of a large scale integrated circuit having a high-level function, an EB tester is indispensable. For detailed defect of a defective device, it is necessary to observe the potential state of an internal circuit and to trace a defective wire by utilizing tools, such as a CAD navigation. Japanese Patent Laying Open Gazette No. P09-054145 discloses a fault diagnostic apparatus for integrated circuits, by employing tools, such as a CAD navigation.
FIG. 12 is a cross-sectional view of a device under test in a conventional measuring method employing an EB tester. A device under test 1 is generally housed in a resin package 2. The device 1 is an integrated circuit formed on an SOI (Silicon On Insulator) substrate. Semiconductors other than silicon may be used for this substrate. An SOI substrate 1s constituting the device 1 comprises a silicon layer 1a of several hundred .mu.m thick, a thin insulating layer 1c, and an SOI layer 1b, which are stacked in this order. To diffusion regions 1e of MOS (Metal Oxide Semiconductor) transistors arranged in a plane on the SOI substrate 1s, electrical connections of various patterns are feasible by a metal wire 1f of a first wiring layer and a metal wire 1g of a second wiring layer. Electrical connection between the integrated circuit and the outside is made through a lead 3.
In a conventional measuring state as shown in FIG. 12, the upside of the resin package 2 (i.e., the side on which the SOI layer 1b is present as viewed from the insulating layer 1c) is unsealed and part of a protection film 1h is removed to expose the metal wire 1g and the like.
FIG. 13 is a schematic diagram showing an example of use of a conventional EB tester. An EB tester 10 has a monitor 10a that displays the potential waveform and potential contrast image of a device under test 1. In order to bring the atmosphere of the device 1 into the vacuum, the device 1 is placed in a vacuum chamber 10b of the EB tester 10. The device 1 is connected to a DUT (Device Under Test) board 12. To display a potential contrast image and the like on the monitor 10a, the device 1 is driven by signals supplied from a bus 11a of a testing set 11 through the DUT board 12. With the device 1 driven, EB 15 is directly irradiated to the device 1 by an EB irradiation unit 13. Unsealing of the upside of the resin package 2, as shown in FIG. 12, permits a direct irradiation of the EB 15 to the device 1. Since part of the protection film 1h formed on the surface of the device 1 is removed so as to reach the metal wires 1f, 1g, it is possible to detect secondary electrons 16 generated when the EB 15 strikes the surfaces of the metal wires 1f, 1g, by a secondary electron detector 14. That is, the potential contrast images of the metal wires 1f, 1g and the like are obtainable by using the device under test 1 as shown in FIG. 12.
In the conventional methods of detecting a defect of a semiconductor integrated circuit and their apparatuses with the above stated construction, it is difficult to trace a defective wire only by the observation of the surface due to the large-scale integration and multi-layer of integrated circuits. In addition, since metal wires are the subject of observation, it is impossible to directly observe at the level of elements constituting an integrated circuit. It is expected that as semiconductor integrated circuits have more large scale, multi-layer and large-scale integration, their fault analyses become more difficult. Therefore, the importance of this problem will raise in the future.